搜索资源列表
keeloq encoder
- this code is a keeloq encryption verilog code-keeloq encryption verilog code
QuadratureCounter
- gdf example for Quadrature Encoder Counter
VD-vhdl-Code
- this codes are for convolution encoder and Viterbi decoder synthesis and implementation.
code
- 详细的解析加代码，是用VHDL写的编码器与解码器的简单应用 -Plus detailed analysis code is written in VHDL encoder and decoder, a simple application
rs(31-19)
- 本源代码是RS（31,19）编码器的顶端实现程序和测试程序，此程序可以验证编码器工作与否。此代码，已在ModelSim验证通过。并附上测试时所产生的结果图像。-Source code is RS (31,19) encoder to achieve the top programs and testing procedures, this program can verify the encoder to work or not. This code has been verified in M
PPM_Coder
- PPM 编码器 按照PPM编码格式编写的普通VHDL代码-PPM PPM encoder encoding format prepared in accordance with the ordinary VHDL code
74-Hamming-code-encoder-and-decoder
- 基于VHDL实现（7，4）汉明码的编码器和译码器-VHDL-based implementation (7,4) Hamming code encoder and decoder
encoder
- 802.11a卷积码的实现，使用公式133和177，可以用标准viterbi解码-802.11a convolutional code to achieve, using the formula 133 and 177, you can use standard viterbi decoding
VHDL
- EDA技术以EDA软件工具为开发环境，以可编程逻辑器件为实验载体，实现源代码编程和仿真功能。VHDL作为一种标准化的硬件描述语言用于描述数字系统的结构、行为、功能和接口。本设计提出了一种基于VHDL语言的编码器和译码器的实现方法。编码器与译码器是计算机电路中基本的器件，本课程设计采用EDA技术设计编码和译码器。编码器由8线-3线优先编码器作为实例代表，译码器则包含3线-8线译码器和2线-4线译码器两个实例模块组成。课程设计采用硬件描述语言VHDL把电路按模块化方式进行设计，然后进行编程、时序仿
Priority-encoder
- 在Quartus II中用VHDL语言编写的优先级编码器程序-In the Quartus II VHDL language using the priority encoder program
ug_rs-compiler
- altera RS编译码器datasheet-the datasheet of the rs encoder and decoder of altera
dvi_encoder_decoder_for---fpga
- dvi encoder and decoder in VHDL for FGPA developer.
Encoder
- VHDL Beispiel für Encoder
encoder
- vhdl program for convolutional encoder and interleaver
encoder
- 使用VHDL编写的光电编码器。并且在quartus软件进行仿真。最终下载在FPGA板上实现光电编码器的使用。-Optical encoder using VHDL written. And quartus software simulation. The final use of photoelectric encoder download FPGA board.
7segment-display-VHDL
- 使用的NEXYS2原型设计电路板的7段编码器模拟-using the NEXYS 2 prototyping board Simulate the 7-segment encoder
8-3-Encoder
- VHDL program for “8:3 Encoder” behavioral design in Xilinx integrated software environment
BCD-ENCODER
- VHDL program for “Decimal To BCD Encoder” behavioral design in Xilinx integrated software environment
BIN-ENCODER
- VHDL program for “Octal To Binary Encoder” behavioral design in Xilinx integrated software environment
PARITY-ENCODER
- VHDL program for “Parity Encoder” behavioral design in Xilinx integrated software environment